1989 | |
| Kadlec J.: Research and Development of Fast Numerically Stable Algorithms for Recursive Identification of Stochastic Systems and their Fixed Point Implementations. (Research Report No. A). Ruhr-Universität, Bochum 1989, 95 pp. | |
| Kadlec J., Krampe G.: Bayesian Analysis of System Parameter Variations, Based on Testing of Hypotheses about Forgetting Factors. (Research Report No. A). Ruhr-Universität, Bochum 1989, 35 pp. | |
| Kadlec J., Stammen P.: Bayesian Recursive Identification of Large Scale Interconnected Stochastic Time Variable Systems, Based on Testing of Hypotheses about Regreession Models. (Research Report No. A). Ruhr-Universität, Bochum 1989, 29 pp. | |
1990 | |
| Kadlec J., Matulík R.: Terminály pro zrakově postižené. (Research Report No. 1691). ÚTIA ČSAV, Praha 1990, 53+příl. pp. | |
1991 | |
| Kadlec J.: A Recursive Modified Gram-Schmidt Identification with Directional Tracking of Parameters. In: Preprints of the 9th IFAC/IFORS Symposium on Identification and System Parameter Estimation. AKA PRINT Nyomdaipari, Budapest 1991, pp. 1707-1712. | |
| Kadlec J.: Fast and Adaptive Identification Algorithms Suitable for Neural Network Applications. In: Neural Nets for System Applications. IEE/ÚTIA, Prague 1991, pp. -. | |
| Kadlec J.: Identification Algorithms for Parallel Computing Networks with Fixed Point Arithmetic. In: Neural Nets for System Applications. IEE/ÚTIA, Prague 1991, pp. -. | |
| Kadlec J. (Ed.): Neural Nets for System Applications. IEE/ÚTIA, Praha 1991, 68 pp. | |
| Kadlec J., Masarik G., Nguyen D. H.: Paralelní počítače a superpočítače dneška. Computer World, 10 (1991), 10, 18-19. | |
1992 | |
| Kadlec J.: A Joint Criterion for Exponential Directional and Mixed Parameter Tracking. In: 4th IFAC International Symposium on Adaptive Systems in Control and Signal Processing. ACASP '92. (Landau I. D., Dugard L., M'Saad M. eds.). Laboratoire d'Automatique, Grenoble 1992, pp. 687-692. | |
| Kadlec J.: Fast Ladder-Lattice Identification Architecture with Numerically Robust Tracking of Parameters. In: Algorithms and Architectures for Real-Time Control. (Fleming P. O., Jones D. I. eds.). ( IFAC Workshop Series. 4). Pergamon Press, Oxford 1992, pp. 105-111. | |
| Kadlec J.: Unified Design of Fast Array Estimators. (Research Report No. 1/6). Queen's University, Belfast 1992, 25 pp. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Parallel Implementation of Restricted Parameter Tracking. In: Mathematics in Signal Processing. University of Warwick, Southend-on-Sea 1992, pp. 86-88. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Regularised Lattice-Ladder Adaptive Filter. In: IFAC Workshop on Mutual Impact of Computing Power and Control Theory. MICC '92. (Kárný M., Warwick K. eds.). ÚTIA ČSAV, Prague 1992, pp. 143-150. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Systolic Implementation of the Regularized Parameter Estimator. In: VLSI Signal Processing 6. (Yao K., Jain R., Przytula W., Rabaey J. eds.). IEEE, New York 1992, pp. 520-529. | |
| Nedoma P., Kadlec J., Schier J.: Tools for Implementation of Parallel Algorithms for Adaptive Control and Signal Processing. In: 4th IFAC International Symposium on Adaptive Systems in Control and Signal Processing. ACASP '92. (Landau I. D., Dugard L., M'Saad M. eds.). Laboratoire d'Automatique, Grenoble 1992, pp. 727-730. | |
1993 | |
| Kadlec J.: Structure Determination and Tracking for Parallel Radial Basis Function Based Nonlinear Networks. In: Innovative Approaches to Modelling and Optimal Control of Large Scale Pipeline Networks. (Králik J. ed.). ÚTIA AV ČR, Prague 1993, pp. 75-84. | |
| Kadlec J.: The Cell Level Description of Systolic Block Regularised QR Filter. In: VLSI Signal Processing. (Eggermont L. D. J., Dewilde P. eds.). IEEE, New York 1993, pp. 298-306. | |
| Kadlec J.: The Lattice-Ladder with Generalized Forgetting. In: Linear Algebra for Large Scale and Real-Time Applications. (Moonen M. S., Golub G. H., De Moor B. L. R. eds.). ( NATO ASI Series. Series E: Applied Sciences. 232). Kluwer Academic, Leuven 1993, pp. 397-398. | |
| Kadlec J.: Transputer Implementation of Block Regularised Filtering. In: Progress in Transputer Computing Technology. (Kulhavá L., Schier J., Kárný M. eds.). ÚTIA AV ČR, Prague 1993, pp. 1-15. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: A Nonlinear Systolic Filter with Radial Basis Function Estimation. In: Neural Computing Research and Applications. (Hilger A. ed.). IOP Publ., London 1993, pp. 183-190. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Parallel Implementation of Restricted Parameter Tracking. (Research Report No. 1/2). Queen's University, Belfast 1993, 17 pp. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Regularised Lattice-Ladder Adaptive Filter. In: Mutual Impact of Computing Power and Control Theory. (Kárný M., Warwick K. eds.). Plenum Press, New York 1993, pp. 245-257. | |
1994 | |
| Gaston F. M. F., Kadlec J., Schier J.: The Block Regularised Linear Quadratic Optimal Controller. (Research Report No. 1789). ÚTIA AV ČR, Praha 1994, 18 pp. | |
| Gaston F. M. F., Kadlec J., Schier J.: The block regularized linear quadratic optimal controller. In: IEE International Conference on Control '94. ( IEE. 389). IEE, London 1994, pp. 1254-1259. | |
| Kadlec J.: Direct Software Bridge MATLAB-Transputer Boards. (Research Report No. 1819). ÚTIA AV ČR, Praha 1994, 4 pp. | |
| Kadlec J.: Direct software bridge MATLAB-transputer boards. In: Signal Processing Conference. Proceedings. (Covan C. F. N. ed.). EUSIPCO, Edinburgh 1994, pp. 1601-1604. | |
| Kadlec J.: Lattice Feedback Regularised Identification. (Research Report No. 1788). ÚTIA AV ČR, Praha 1994, 30 pp. | |
| Kadlec J.: Lattice feedback regularised identification. In: 10th IFAC Symposium on System Identification. Preprints. (Blanke M., Söderström T. eds.). IFAC, Copenhagen 1994, pp. 277-282. | |
| Kadlec J.: Matlab transputer bridge. Abstract. In: 10th IFAC Symposium on System Identification. Preprints. (Blanke M., Söderström T. eds.). IFAC, Copenhagen 1994, pp. 31. | |
| Kadlec J.: Numerical Analysis of a Normalized RLS Filter Using a Probability Description of Propagated Data. (Research Report No. 1818). ÚTIA AV ČR, Praha 1994, 12 pp. | |
| Kadlec J.: Numerical analysis of normalized RGS filter by probability description of propagated data. Abstract. In: Algorithms and Parallel VLSI Architectures. Abstracts. Katholieke Universiteit, Leuven 1994, pp. -. | |
| Kadlec J.: Numerical analysis of normalized RLS filter using a probability description of propagated data. In: Algorithms and Parallel VLSI Architectures III. (Moonen M., Catthor F. eds.). Elsevier, Amsterdam 1994, pp. 61-72. | |
| Kadlec J.: Parallel Normalized Identification Algorithm with Lattice Feedback Regularization. (Research Report No. 1820). ÚTIA AV ČR, Praha 1994, 35 pp. | |
| Kadlec J.: Structure Determination and Tracking for Parallel Radial Basic Function Based Nonlinear Networks. (Research Report No. 1790). ÚTIA AV ČR, Praha 1994, 13 pp. | |
| Kadlec J.: Systolic Arrays for Identification of Systems with Variable Structure. (Research Report No. 1817). ÚTIA AV ČR, Praha 1994, 10 pp. | |
| Kadlec J.: Systolic arrays for identification of systems with variable structure. In: Computer-Intensive Methods in Control and Signal Processing. (Kulhavá L., Kárný M., Warwick K. eds.). ÚTIA AV ČR, Praha 1994, pp. 123-132. | |
| Kadlec J.: The Cell-Level Description of Systolic Block Regularised QR Filter. (Research Report No. 1792). ÚTIA AV ČR, Praha 1994, 10 pp. | |
| Kadlec J.: Transputer Implementation of Block Regularised Filtering. (Research Report No. 1791). ÚTIA AV ČR, Praha 1994, 16 pp. | |
| Kadlec J.: [Recenze]. (Nocetti D. F. G., Fleming P. J.: Parallel Processing in Digital Control.) Automatica 30 (1994), 5, 917-918. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Parallel implementation of restricted parameter tracking. In: Mathematics in Signal Processing. (McWhirter J. G. ed.). ( Institute of Mathematics and its Applications Conference Series. 49). Clarendon Press, Oxford 1994, pp. 315-325. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: Regularised Lattice-Ladder Adaptive Filter. (Research Report No. 1793). ÚTIA AV ČR, Praha 1994, 19 pp. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: The Block Regularised Parameter Estimator and Its Parallel Implementation. (Research Report No. 1787). ÚTIA AV ČR, Praha 1994, 33 pp. | |
1995 | |
| Kadlec J.: [Recenze]. (Kalouptsidis N., Theodoridis S.: Adaptive System Identification and Signal Processing Algorithms.) Automatica 31 (1995), 10, 1519-1521. | |
| Kadlec J., Gaston F. M. F.: Identification with directional parameter tracking for high-performance fixed-point implementations. In: The Sixth Irish DSP and Control Colloquium. (Gaston F., Dodds G. eds.). Techman, Belfast 1995, pp. 215-222. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: The block regularised parameter estimator and its parallelisation. Automatica, 31 (1995), 8, 1125-1136. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: The block regularised parameter estimator and its parallelisation. In: Identification and Optimization, Oriented for Use in Adaptive Control. Preprints. (Böhm J., Rojíček J. eds.). ÚTIA AV ČR, Praha 1995, pp. 107-120. | |
| Kadlec J., Nakhaee N.: Alpha Bridge - high performance computing with MATLAB. In: Industrial Applications of MATLAB and Simulink for the Analysis of Electro- and Hydro- Mechanical Systems. Preprints. Matlab UG, Birmingham 1995, pp. 11-16. | |
| Kadlec J., Nakhaee N.: Alpha-Bridge for MATLAB 4. In: Transputer Applications and Systems '95. Proceedings. (Cook B. M., Nixon P. eds.). IOS Press, Harrogate 1995, pp. 175-189. | |
| McWhirter J. G., Walke R. L., Kadlec J.: Normalised Givens rotations for recursive least squares processing. In: VLSI Signal Processing, VIII. (Nishitani T., Parhi K. eds.). IEEE, New York 1995, pp. 313-322. | |
1996 | |
| Kadlec J.: Transputer implementation of block regularized filtering. Kybernetika, 32 (1996), 3, 235-250. | |
| Nedoma P., Kadlec J.: Extension of MATLAB parallel accelerator. In: Computer-Intensive Methods in Control and Signal Processing. Preprints of the 2nd European IEEE Workshop CMP'96. (Berec L., Rojíček J., Kárný M., Warwick K. eds.). ÚTIA AV ČR, Praha 1996, pp. 155-160. | |
1997 | |
| Kadlec J.: Para-Mat parallel processing under MATLAB. In: Simulationstechnik. Tagungsband. (Kuhn A., Wenzel S. eds.). ( ASIM 11). Vieweg, Braunschweig 1997, pp. 684-687. | |
| Kadlec J.: Parallel processing on Alphas under MATLAB 5. In: SOFSEM '97: Theory and Practice of Informatics. (Plášil F., Jeffery K. G. eds.). ( Lecture Notes in Computer Science. 1338). Springer, Berlin 1997, pp. 440-448. | |
| Kadlec J.: Rapid prototyping and parallel processing under MATLAB 5. In: Tagungsband. 3. Zittauer Workshop Magnetlagertechnik. (Hampel R., Worlitz F. eds.). ( Wissenschftliche Berichte. 51). IPM, Zittau 1997, pp. 101-104. | |
| Kadlec J., Gaston F. M. F., Irwin G. W.: A parallel fixed-point predictive controller. International Journal of Adaptive Control and Signal Processing, 11 (1997), 5, 415-430. | |
| Kadlec J., Vialatte C.: Rapid prototyping and parallel processing under MATLAB 5. In: MATLAB Conference 1997. Kimhua Technology, Seoul 1997, pp. 120-125. | |
1998 | |
| Kadlec J.: Acceleration of computation-intensive algorithms on parallel Alpha AXP processors. In: Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing. (Rojíček J., Valečková M., Kárný M., Warwick K. eds.). ÚTIA AV ČR, Praha 1998, pp. 89-98. | |
| Kadlec J., Schier J.: HSLA 3D Monitor Package. (Research Report No. 1925). ÚTIA AV ČR, Praha 1998, 51 pp. | |
| Kadlec J., Schier J.: HSLA DSP Package. (Research Report No. 1924). ÚTIA AV ČR, Praha 1998, 12 pp. | |
| Kadlec J., Schier J.: Numerical Analysis of a Normalized QR Filter Using Probability Description of Propagated Data. (Research Report No. 1923). ÚTIA AV ČR, Praha 1998, 23 pp. | |
| Kadlec J., Schier J.: Rapid prototyping of adaptive control algorithms on parallel multiprocessors. In: Signal Processing Symposium. IEEE, Leuven 1998, pp. 115-118. | |
| Kadlec J., Schier J.: Results of the Global Probability Analysis Approach. (Research Report No. 1926). ÚTIA AV ČR, Praha 1998, 89 pp. | |
| Kárný M., Kadlec J., Sutanto E. L.: Quasi-Bayes estimation applied to normal mixture. In: Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing. (Rojíček J., Valečková M., Kárný M., Warwick K. eds.). ÚTIA AV ČR, Praha 1998, pp. 77-82. | |
| Schier J., Kadlec J., Böhm J.: Robust adaptive controller with fine grain parallelism. In: Preprints of the IFAC Workshop on Adaptive Systems in Control and Signal Processing. IFAC, Glasgow 1998, pp. 436-441. | |
1999 | |
| Hillerová E., Kadlec J. (Eds.): Czech Republic, Information Society Technology. ÚTIA AV ČR, Praha 1999, 186 pp. | |
| Hillerová E., Kadlec J. (Eds.): Informační den k programu IST. Technologické centrum AV ČR, Praha 1999, 103 pp. | |
| Hillerová E., Kadlec J. (Eds.): Konference k zahájení 5. rámcového programu Evropské unie. MŠMT, Praha 1999, 90 pp. | |
| Kadlec J., Barbier A., de Castellane L., Gautier L., Gourguechon S., Leroy S., Paturle A.: Generation of Simulink S-functions. (Research Report No. 1975). ÚTIA AV ČR, Praha 1999, 199 pp. | |
| Kadlec J., Matoušek R., Vialatte C., Coleman J. N.: Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW. In: Sborník příspěvků 7. ročníku konference MATLAB '99. VŠCHT, Praha 1999, pp. 84-90. | |
| Kadlec J., Schier J.: Analysis of a normalized QR filter using Bayesian description of propagated data. International Journal of Adaptive Control and Signal Processing, 13 (1999), 6, 487-505. | |
| Tesař L., Berec L., Dolanc G., Szederkényi G., Kadlec J.: A toolbox for model-based fault detection and isolation. In: European Control Conference. ECC '99. VDI/VDE GMA, Karlsruhe 1999, 410 kB. | |
| Vialatte C., Kadlec J.: RTW support for low cost C31 board. In: Sborník příspěvků 7. ročníku konference MATLAB '99. VŠCHT, Praha 1999, pp. 231-237. | |
| Vialatte C., Kadlec J.: RTW support for parallel 64-bit Alpha AXP-based platforms. In: Sborník příspěvků 7. ročníku konference MATLAB '99. VŠCHT, Praha 1999, pp. 238-244. | |
2000 | |
| Coleman J. N., Chester E. I., Softley C. I., Kadlec J.: Arithmetic on the European Logarithmic Microprocessor. IEEE Transactions on Computers, 49 (2000), 7, 702-715. | |
| Heřmánek A., Matoušek R., Líčko M., Kadlec J.: FPGA implementation of logarithmic unit. In: Sborník příspěvků 8. ročníku konference MATLAB 2000. VŠCHT, Praha 2000, pp. 84-90. | |
| Hlavička J., Kadlec J.: Vstup českých institucí do evropské informační společnosti. In: Česko-slovenská konference RUFIS 2000. VUT, Brno 2000, pp. 27-32. | |
| Hlavička J., Kadlec J.: Vstup do evropské informační společnosti - program IST. Automa, 6 (2000), 7, 105-107. | |
| Kadlec J.: Konkrétní příležitost pro firmy z ČR: Projekty take-up programu IST s termínem podání 31.10.2000. Automa, 6 (2000), 7, 104. | |
| Ondračka J., Oravec R., Kadlec J., Cocherová E.: Simulation of RLS and LMS algorithms for adaptive noise cancellation in MATLAB. In: Sborník příspěvků 8. ročníku konference MATLAB 2000. VŠCHT, Praha 2000, pp. 301-305. | |
| Schier J., Kadlec J., Moonen M.: Implementing advanced equalization algorithms using Simulink with embedded Alpha AXP coprocessor. In: Fifth IMA International Conference on Mathematics in Signal Processing. University of Warwick, Warwick 2000, pp. 11-14. | |
2001 | |
| Albu F., Kadlec J., Fagan A., Coleman J. N.: Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic. In: Advances in Systems Science: Measurement, Circuits and Control. Proceedings. (Mastorakis N. E., Pecorelli-Peres L. A. eds.). WSES Press, Rethymno 2001, pp. 517-521. | |
| Albu F., Kadlec J., Matoušek R., Heřmánek A., Coleman J. N.: A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic. (Research Report No. 2035). ÚTIA AV ČR, Praha 2001, 5 pp. | |
| Albu F., Kadlec J., Softley C., Matoušek R., Heřmánek A.: Implementation of Normalized RLS Lattice on Virtex. (Research Report No. 2040). ÚTIA AV ČR, Praha 2001, 10 pp. | |
| Albu F., Kadlec J., Softley C., Matoušek R., Heřmánek A., Coleman J. N., Fagan A.: Implementation of (Normalised) RLS Lattice on Virtex. In: Field-Programmable Logic and Applications. Proceedings. (Brebner G., Woods R. eds.). ( Lecture Notes in Computer Science. 2147). Springer, Berlin 2001, pp. 91-100. | |
| Coleman J. N., Chester E. I., Softley C., Kadlec J.: Arithmetic on the European Logarithmic Microprocessor. (Research Report No. 2012). ÚTIA AV ČR, Praha 2001, 4 pp. | |
| Coleman J. N., Kadlec J.: Extended Precision Logarithmic Arithmetic. In: Signal Systems and Computers 2000, 34th Asilomar Conference on Signal Systems and Computers. Proceedings. IEEE Signal Processing Society, Monterey 2001, pp. 124-129. | |
| Coleman J. N., Kadlec J., Matoušek R., Pohl Z., Heřmánek A.: The European Logarithmic Microprocessor - a QRD RLS Applications. (Research Report No. 2038). ÚTIA AV ČR, Praha 2001, 9 pp. | |
| Heřmánek A., Kadlec J., Matoušek R., Líčko M., Pohl Z.: Pipelined logarithmic 32bit ALU for Celoxica DK1. In: Sborník příspěvků 9.ročníku konference MATLAB 2001. (Procházka A., Uhlíř J. eds.). VŠCHT, Praha 2001, pp. 72-80. | |
| Heřmánek A., Kadlec J., Matoušek R., Líčko M., Softley C.: Pipelined Logarithmic 32bit ALU for Celoxica DK1. (Research Report No. 2034). ÚTIA AV ČR, Praha 2001, 11 pp. | |
| Kadlec J.: Review and Classification of RLS Array Algorithms for LNS Arithmetics. (Research Report No. 2006). ÚTIA AV ČR, Praha 2001, 18 pp. | |
| Kadlec J.: Structure estimation for systems described by radial basis functions based on normalized QR filtering. In: Preprints of the 1st IFAC/IEEE Symposium on System Structure and Control. IFAC, Prague 2001, 140 kB. | |
| Kadlec J., Albu F., Softley C., Matoušek R., Heřmánek A.: RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic. (Research Report No. 2036). ÚTIA AV ČR, Praha 2001, 11 pp. | |
| Kadlec J., Coleman J. N.: Extended Precision LNS Arithmetic. (Research Report No. 2008). ÚTIA AV ČR, Praha 2001, 15 pp. | |
| Kadlec J., Heřmánek A., Softley C., Matoušek R., Líčko M.: 32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1. (Research Report No. 2037). ÚTIA AV ČR, Praha 2001, 12 pp. | |
| Kadlec J., Heřmánková D., Rektorová A., Drath P., Schoefield M., Martynovicz P.: Uspořádání VT akce : Opportunities in the European Union's IST Programme. Praha, 01.11.13-01.11.14. | |
| Kadlec J., Heřmánková D., Trojanowski K., Drath P., Schoefield M., Burak R.: Uspořádání VT akce : Managing EC Research Project - Workshop and Brokerage. Praha, 01.12.11. | |
| Kadlec J., Kadlecová M., Pleger R., Grabowiecki T., Zergoi T., Krekels D.: Uspořádání VT akce : Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing. Praha, 01.09.26. | |
| Kadlec J., Matoušek R., Heřmánek A., Líčko M., Softley C.: Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1. In: Celoxica User Conference. Proceedings. Celoxica, Abington 2001, 202 kB. | |
| Kadlec J., Matoušek R., Líčko M.: FPGA implementation of logarithmic unit core. In: Embedded Intelligence 2001. Design & Elektronik, Nürnberg 2001, pp. 547-554. | |
| Kadlec J., Matoušek R., Líčko M.: FPGA Implementation of Logarithmic Unit Core. (Research Report No. 2007). ÚTIA AV ČR, Praha 2001, 8 pp. | |
| Pleger R., Kadlec J., Grabowiecki T., Kadlecová M., Krekels D., Heřmánek A.: Uspořádání VT akce : Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing. Dresden, 01.09.17. | |
| Schier J., Kadlec J., Moonen M.: Implementing Advanced Equalization Algorithms using Simulink with Embedded Alpha AXP Coprocessor. (Research Report No. 2013). ÚTIA AV ČR, Praha 2001, 4 pp. | |
2002 | |
| Albu F., Kadlec J., Coleman N., Fagan A.: Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic. In: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing. IEEE, Orlando 2002, pp. 2681-2684. | |
| Albu F., Kadlec J., Coleman N., Fagan A.: The Gauss-Seidel Fast Affine Projection algorithm. In: IEEE Workshop on Signal Processing Systems. Proceedings. (Parhi K., Shanbhag N. eds.). IEEE, San Diego 2002, pp. 109-114. | |
| Albu F., Kadlec J., Heřmánek A., Fagan A., Coleman N.: Analysis of the LNS implementation of the fast affline projection algorithms. In: Proceedings of the Irish Signals and Systems Conference 2002. ISSC 2002. (Marnane W., Lightbody G., Pesch D. eds.). Institute of Technology, Cork 2002, pp. 251-255. | |
| Grabowiecki T., Kadlec J., Čerans K., Pihl T., Weber B., Zergoi T.: Uspořádání VT akce : Ideal-ist Conference Information Society Technology in the 6th Framework Programme. Varšava, 02.11.25-02.11.26. | |
| Kadlec J., Matoušek R., Heřmánek A., Líčko M., Tichý M.: Lattice for FPGAs using logarithmic arithmetic. Electronic Engineering Design, 74 (2002), 906, 53-56. | |
| Kadlec J., Tichý M., Heřmánek A., Pohl Z., Líčko M.: Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs. In: Design, Automation and Test in Europe DATE˙02. (Sciuto D., Kloos C. D. eds.). IEEE, Los Alamitos 2002, pp. 264. | |
| Líčko M., Schier J., Pohl Z., Kadlec J., Tichý M., Matoušek R., Heřmánek A.: Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping. (Research Report No. 2069). ÚTIA AV ČR, Praha 2002, 7 pp. | |
| Matoušek R., Pohl Z., Kadlec J., Tichý M., Heřmánek A.: Logarithmic arithmetic core based RLS LATTICE implementation. In: Design, Automation and Test in Europe DATE 02. (Sciuto D., Kloos C. D. eds.). IEEE, Los Alamitos 2002, pp. 271. | |
| Matoušek R., Tichý M., Pohl Z., Kadlec J., Softley C.: Logarithmic number system and floating-point arithmetics on FPGA. In: Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. (Glesner M., Zipf P., Renovell M. eds.). ( Lecture Notes in Computer Science. 2438). Springer, Berlin 2002, pp. 627-636. | |
| Smith B., Edin M., Hillerová E., Kadlecová M., Heřmánková D., Kadlec J.: Uspořádání VT akce : e-2002 e-Work & e-Business Conference. Praha, 02.10.16-02.10.18. | |
2003 | |
| Heřmánek A., Pohl Z., Kadlec J.: FPGA implementation of the adaptive lattice filter. In: Field-Programmable Logic and Applications. Proceedings of the 13th International Conference. (Cheung P. Y. K., Constantinides G. A., de Sousa J. D. eds.). ( Lecture Notes in Computer Science. 2778). Springer, Berlin 2003, pp. 1095-1098. | |
| Líčko M., Kadlec J.: An Introduction to the Xilinx System Generator. (Program). ÚTIA AV ČR, Praha 2003, 67.3 MB. | |
| Líčko M., Matulík R., Matoušek R., Kadlec J.: Prototyping Board for CAK. (Program). ÚTIA AV ČR, Praha 2003, 150 MB. | |
| Matoušek R., Daněk M., Pohl Z., Kadlec J.: Dynamic runtime partial reconfiguration in FPGA. In: ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals. (Nouza J., Drábková J. eds.). Technical University, Liberec 2003, pp. 294-298. | |
| Matoušek R., Líčko M., Kadlec J.: European Logarithmic Microprocessor. (Program). ÚTIA AV ČR, Praha 2003, 46.5 MB. | |
| Matoušek R., Pohl Z., Daněk M., Kadlec J.: Dynamic reconfiguration of Atmel FPGAs. In: UK ACM SIGDA 3rd Workshop on Electronic Design Automation. (Hettiaratchi S. ed.). University of Southampton, Southampton 2003, pp. 1-4. | |
| Matoušek R., Pohl Z., Daněk M., Kadlec J.: Dynamic reconfiguration of FPGAs. In: Recent Trends in Multimedia Information Processing. Proceedings. (Šimák B., Zahradník P. eds.). Czech Technical University, Prague 2003, pp. 288-291. | |
| Pohl Z., Kadlec J., Líčko M., Matoušek R., Tichý M.: Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program). ÚTIA AV ČR, Praha 2003, 32 MB. | |
| Pohl Z., Kadlec J., Tichý M.: RLS Lattice - Celoxica RC200 Demo. (Program). ÚTIA AV ČR, Praha 2003, 31.5 MB. | |
| Pohl Z., Matoušek R., Kadlec J., Tichý M., Líčko M.: Lattice adaptive filter implementation for FPGA. In: FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays. ACM, Monterey 2003, pp. 246. | |
| Schier J., Kadlec J.: Using logarithmic arithmetic for FPGA implementation of the Givens rotations. In: Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications. (Mosquera C., Perez-Gonzales F. eds.). Universidade de Vigo, Vigo 2003, pp. 199-204. | |
2004 | |
| Daněk M., Honzík P., Kadlec J., Matoušek R., Pohl Z.: Reconfigurable system-on-a-programmable-chip platform. In: Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. (Peng Z., Fischerová M., Gramatová E. eds.). Institute of Informatics SAS, Bratislava 2004, pp. 21-28. | |
| Kadlec J.: IDEALIST: Jak najít partnery pro projekty IST. Echo, - (2004), 3, 13. | |
| Kadlec J., Daněk M., Honzík P.: Reconfigurable 24-Bit Floating-Point Coprocessor Demo. (Research Report No. 2116). ÚTIA AV ČR, Praha 2004, 9 pp. | |
| Kadlec J., Daněk M., Honzík P.: Reconfigurable Scrolling Demo. (Research Report No. 2117). ÚTIA AV ČR, Praha 2004, 3 pp. | |
| Kadlec J., Kadlecová M.: Uspořádání VT akce : Workshop FET. Future and Emerging Technologies in the frame of IST FP6. Praha, 04.05.14. | |
2005 | |
| Daněk M., Heřmánek A., Honzík P., Kadlec J., Matoušek R., Pohl Z.: GIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs. In: ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems. (Bosschere K. ed.). HiPEAC Network of Excellence, Ghent 2005, pp. 15-18. | |
| Daněk M., Honzík P., Kadlec J., Matoušek R., Pohl Z.: Reconfigurable system on programmable chip platform. ATMEL Applications Journal (2005), 4, 9-12. | |
| Kadlec J.: Double Precision Simulation Package double-dk-rel2. (Program). ÚTIA AV ČR, Praha 2005, 2.64 MB. | |
| Kadlec J.: Reconfigurable floating point co-processor for atmel FPSLIC. In: MAPLD 2005 International Conference Proceedings. (Katz R. B. ed.). NASA Office of Logic Design, Washington 2005, pp. 1-12. | |
| Kadlec J.: Scalable Floating Point Simulation Package float-dk-rel2. (Program). ÚTIA AV ČR, Praha 2005, 4.98 MB. | |
| Kadlec J., Albrecht V.: Význam účasti v projektech EU. Echo, 2 (2005), 2, 11-13. | |
| Kadlec J., Gook R.: Floating point controller as a picoblaze network on a single spartan 3 FPGA. In: MAPLD 2005 International Conference Proceedings. (Katz R. B. ed.). NASA Office of Logic Design, Washington 2005, pp. 1-11. | |
| Kadlec J., Kadlecová M.: Uspořádání VT akce : Výměna zkušeností řešitelů evropských projektů po 1. kole auditů 6. RPEU. Praha, 05.11.03. | |
| Pohl Z., Kadlec J., Šůcha P., Hanzálek Z.: Performance tuning of iterative algorithms in signal processing. In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. (Rissa T., Wilton S., Leong P. eds.). Academy of Finland, Tampere 2005, pp. 699-702. | |
2006 | |
| Daněk M., Honzík P., Kadlec J., Pohl Z., Matoušek R.: Platforma s částečnou dynamickou rekonfigurací FPGA. Automa, 12 (2006), 5, 40-43. | |
| Kadlec J., Chappel S.: Implementing floating-point DSP. Embedded Magazine, 2 (2006), 3, 12-14. | |
| Kadlec J., Daněk M.: Design and verification methodology for reconfigurable designs in Atmel FPSLIC. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. (Reorda M. S., Novák O., Straube B. eds.). Czech Technical University, Prague 2006, pp. 79-80. |