Institute of Information Theory and Automation

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Placement and Routing for Dynamic Reconfiguration in FPGAs

Ing. Petr Honzík
Defense type: 
Date of Event: 
FEL ČVUT, Karlovo nám. 13, Praha 2, 121 35
The work deals with reconfigurable systems with self adaptivity based on the FPGA platform. The thesis consists of three parts. The first part deals with partial dynamic reconfiguration on the FPGA devices. The possibility of the dynamic reconfiguration in the reconfigurable systems and its space complexity is analyzed. The function density that expresses an application performance running in a dynamic module is presented. Further the text presents reconfigurable hardware platforms available on today’s market and the methodology how to implement the reconfigurable flow and the reconfigurable hardware. It introduces a reconfiguration controller and its features necessary to control the reconfiguration process and store configuration bitstreams in an external memory. The problems with connections between a static and dynamic parts of the design during reconfiguration is presented. The two reconfigurable coprocessors with an identical function on Virtex from Xilinx and on AT94K FPSLIC from Atmel have been implemented. The comparison of these two implementations is done. The second part analyses self adaptive systems, their elements and features. The analysis of the requirements of the self adaptive system is done with respect to the future implementation on the reconfigurable platforms based on the FPGA devices. An introduction of principles of the self adaptive element that is the basic building block of our adaptive system is done. There is a brief description of the four main blocks of the self adaptive element and their interaction with the environment. The next part describes an implementation of a self adaptive ring network with four self adaptive elements. The simulation of the self adaptive features of the network is done. The third part introduces a network on chip, analyzes it from the side of communication and hardware cost and data stream processing. The stress is put on restrictions due to the FPGA technology. The 2D-Mesh topology was chosen as the most suitable topology for the future simulation of the self adaptive system. Three routing algorithms and their impact to full loading network in the 2D-Mesh network are presented. The following text describes three placement algorithms and the Step-Adaptive Algorithm for improving the placement of running applications on the network and optimization criteria are defined. The simulation framework is used to test the features of the self adaptive system on test cases. The result of the simulations on the self adaptive system compares the Step-Adaptive Algorithm and the presented placement algorithms.
2018-05-03 08:01